Analog /Layout engineers (Hyderabad & Bangalore) Experience: 2+ years

Analog /Layout engineers (Hyderabad & Bangalore) Experience: 2+ years Education: BE/ME/B.Tech/M.Tech in EEE/ECE/EI/CS Job Description: 1. Specification study, Verification Plan Development for Analog/Mixed Signal blocks 2. Block Modelling and Verification in Verilog-AMS 3. Chip Top level Functional Simulation 4. Sign-off against Checklist before Tape Out release Desired Skills & Experience 1. Prior Analog Verification Experience up to 4 Years 2. Analog Circuit Design knowledge and/or experience 3. Experience in Verilog-AMS/Verilog A/VHDL-AMS/Verilog/SV 4. Experience in using Cadence Schematic Editor, ADE in a hands-on manner 5. Mixed Signal Verification Immediate joinees are preferred, 15-days/1-month is still acceptable. If you are interested please share updated profile