If any one interested for the below position, please send your resumes to me.
Email :kishore.soma@gmail.com
Preferred Qualifications:
3 to15 years of industry experience in one or more of the following technical areas:
Power-aware yield estimation
Vmin optimization
Power recovery
Technology comparison PPA analysis and sweeps
Semicustom design of structured blocks
Clock tree analysis and optimization
Library analysis and evaluations
Timing analysis methodologies
Responsibilities:
You will be part of a team responsible for the complete Physical Design Flow for MSM/MDM/CSM chips. Tasks involved can be one or more of the following:
Work with the RTL design team on understanding design in context of physical design timing closure including development of timing constraints required for implementation.
Work with the DFT team on understanding DFT design in regards to physical design timing closure.
Lead core and Top level timing closure activities.
Develop new scripts/flows to improve the timing closure process.
Complete Physical Implementation of cores i.e. graphics, video, multimedia, processor, DDR.
Low-power implementation methods.
Core and Top level Floorplanning, placement, CTS, P&R, PV, and Signal Integrity Analysis.
Develop high speed customized logic cells.
Skills/Experience:
3 to15 years of industry experience in the following technical areas:
Physical design implementation (Floorplanning, CTS, STA) for CPUs and GPUs in advanced technologies.
STA tool and timing closure methodologies
Power grid, clock tree, and low-power reduction implementation methods
Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing
Floorplanning, Placement, CTS
Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification
Programming and scripting skills (Tcl, perl and/or C)
Strong verbal and written communication skills
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