Some requirment for Testing with 2 to 3.5yrs exp
contract position.
Good exposure to Manual, selenium Testing.
good Knowledge on APPiUM/JMETER added Advantage..
9 May 2017
HOT JOBS - Physical Design @ Qualcomm - Bangalore
Preferred Qualifications:
3 to15 years of industry experience in one or more of the following technical areas:
Power-aware yield estimation
Vmin optimization
Power recovery
Technology comparison PPA analysis and sweeps
Semicustom design of structured blocks
Clock tree analysis and optimization
Library analysis and evaluations
Timing analysis methodologies
Responsibilities:
You will be part of a team responsible for the complete Physical Design Flow for MSM/MDM/CSM chips. Tasks involved can be one or more of the following:
Work with the RTL design team on understanding design in context of physical design timing closure including development of timing constraints required for implementation.
Work with the DFT team on understanding DFT design in regards to physical design timing closure.
Lead core and Top level timing closure activities.
Develop new scripts/flows to improve the timing closure process.
Complete Physical Implementation of cores i.e. graphics, video, multimedia, processor, DDR.
Low-power implementation methods.
Core and Top level Floorplanning, placement, CTS, P&R, PV, and Signal Integrity Analysis.
Develop high speed customized logic cells.
Skills/Experience:
3 to15 years of industry experience in the following technical areas:
Physical design implementation (Floorplanning, CTS, STA) for CPUs and GPUs in advanced technologies.
STA tool and timing closure methodologies
Power grid, clock tree, and low-power reduction implementation methods
Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing
Floorplanning, Placement, CTS
Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification
Programming and scripting skills (Tcl, perl and/or C)
Strong verbal and written communication skills
Urgent Req on MS Power BI in Bangalore with 4 to 6 yrs exp _Contract position.
Urgent Req on MS Power BI in Bangalore with 4 to 6 yrs exp _Contract position. Job Description :- . Expertise in BI concepts(including Star, Snowflake and cubes) . Have significant experience working on MSBI stack . Good at Data modelling . Adequate knowledge on Power Query/DAX expressions. . Preferred if worked on either SSAS multi-dim/tabular or Powerpivot. . Experience in creating metrics and visualizations in PowerBI. . Create and publish PowerBI Report Content Packs. . Exposure to Azure BI components
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Urgent Req for testing with 4 to 7yrs in pune location ,contract to hire
Looking for Testers into QTP
Experience: 4 + Years
Job Location: Pune Hinjewadi
Job Description:
· Need QTP/UFT Automation Tester. Basic Selenium knowledge is plus point.
· Resource should be ready to work as Functional tester at time when client demands.
Looking for nutrition and dietition in Delhi
We are looking freshers for the post of nutrition & dietitian in Delhi at Rajouri garden ,If interested Please give us a call or share your profile.
Qualification - BSC/MSC
Physical Design Team is Hiring!!!
If any one interested for the below position, please send your resumes to me.
Email :kishore.soma@gmail.com
Preferred Qualifications:
3 to15 years of industry experience in one or more of the following technical areas:
Power-aware yield estimation
Vmin optimization
Power recovery
Technology comparison PPA analysis and sweeps
Semicustom design of structured blocks
Clock tree analysis and optimization
Library analysis and evaluations
Timing analysis methodologies
Responsibilities:
You will be part of a team responsible for the complete Physical Design Flow for MSM/MDM/CSM chips. Tasks involved can be one or more of the following:
Work with the RTL design team on understanding design in context of physical design timing closure including development of timing constraints required for implementation.
Work with the DFT team on understanding DFT design in regards to physical design timing closure.
Lead core and Top level timing closure activities.
Develop new scripts/flows to improve the timing closure process.
Complete Physical Implementation of cores i.e. graphics, video, multimedia, processor, DDR.
Low-power implementation methods.
Core and Top level Floorplanning, placement, CTS, P&R, PV, and Signal Integrity Analysis.
Develop high speed customized logic cells.
Skills/Experience:
3 to15 years of industry experience in the following technical areas:
Physical design implementation (Floorplanning, CTS, STA) for CPUs and GPUs in advanced technologies.
STA tool and timing closure methodologies
Power grid, clock tree, and low-power reduction implementation methods
Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing
Floorplanning, Placement, CTS
Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification
Programming and scripting skills (Tcl, perl and/or C)
Strong verbal and written communication skills
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